/******************************************************************************
 *
 *                               Sio_fx200
 *
 * This module contains the serial I/O driver for the FX200 UART.
 *
 * History:
 *   +----------+------------+------------------------------------------------+
 *   |   Date   |     by     |     Description                                |
 *   +----------+------------+------------------------------------------------+
 *   |          |            | Written                                        |
 *   +----------+------------+------------------------------------------------+
 * 
 * Uart is defined as array of volatile bytes.
 * The registers are defined as constants elments of the array.
 * 
 *****************************************************************************/
 

#define	UCNTL	0x1	/* control register 	    */
#define	USTAT	0x5	/* status register	    */
#define	UCLST	0x7	/* clearing status register     */
#define	UBRGL	0x9	/* CTTL clock divider low byte  */
#define	UBRGH	0xB	/* CTTL clock divider high byte */
#define	URXB	0xD	/* reception data buffer    */
#define	UTXB	0xF   	/* transmitted data buffer  */

#define PAMS	0x24	/* port module register		*/
#define PCMS	0x34	/* port module register		*/
#define PCEN	0x38	/* port module register		*/

#define UART  ((volatile byte *) UART_0_ADDR)
#define PORT_MOD  ((volatile byte *) 0xfe0800)

/* Primitive macros requierd by sio_d.c */
/****************************************/
 
#define READ_CHAR_IS_READY(dummy_port)  (BIT_ON(0,UART[USTAT]))
#define GET_CHAR(dummy_port)	(UART[URXB])
#define READY_TO_WRITE_CHAR(dummy_port)  (BIT_ON(7,UART[USTAT]))
#define PUT_CHAR(dummy_port,ch)    UART[UTXB] = ch

#define DIVISOR(divisor,  port) divisor = ((unsigned) UART[UBRGL] + \
					((unsigned) UART[UBRGH] << 8))


/*****************************************************************************
 *
 *	init_uart()
 *
 ****************************************************************************/
    
    
private void init_uart(dummy_port, divisor, dummy_mode)
    unsigned int dummy_port, divisor, dummy_mode;
{
    char    ch = 0;

	PORT_MOD[PAMS] |= 0x02;	/* Set port module uart rilated bits to    */
	PORT_MOD[PAMS] &= 0xfe;	

	PORT_MOD[PCMS] |= 0x40; /* proper mode				   */
	PORT_MOD[PCMS] &= 0x7f;

	PORT_MOD[PCEN] |= 0x40;
	PORT_MOD[PCEN] &= 0x7f;

	UART[UBRGL] = (byte) (divisor & 0xff);
	UART[UBRGH] = (byte) ((divisor >> 8)  & 0xff);
	UART[UCNTL] = 0x4; 	/* 8 bits, 1 stop bit, no parity ,no break */
	UART[UCLST] = ch;	/* Clear USTAT overrun error bit	   */
	UART[UCLST] = ch;	/* Clear USTAT overrun error bit	   */
	ch = UART[UCLST];	/* Clear USTAT parity and frame error bits */ 
	ch = UART[UCLST];	/* Clear USTAT parity and frame error bits */ 
	ch = UART[URXB]; 	/* read recive data reg` to flush the uart */
	ch = UART[URXB]; 	/* read recive data reg` to flush the uart */

        DELAY(10000);
}


